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Domains: Digital Circuits, Verilog Programming, Graphics on FPGA
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https://github.com/Harshit6-b/SRA-FPGA-based-tetris
This project implements the classic game Tetris entirely in hardware on an FPGA. All functions—block falling, collision detection, video output, and memory handling—are written in Verilog HDL, with no external CPU.
We first attempted HDMI output, generating TMDS-encoded signals verified on the oscilloscope. However, the monitor failed to sync due to strict timing requirements. For a reliable demo, we switched to VGA, which is simpler and more tolerant. The final system runs Tetris with stable VGA display, proving an FPGA can handle both game logic and real-time graphics.
https://media.discordapp.net/attachments/1387068971282468894/1420263435010052146/VID_20250920_004334.mp4?ex=68d61466&is=68d4c2e6&hm=b961fe634293ed9c2311e37a13b2e9b73bc156b5590168d5a190a1292d613805&
FPGA LUTs, BRAMs execute game pipeline in real time.
Verilog HDL FSMs, counters, and registers designed as hardware.
Counters: VGA pixel clock & sync. Combinational logic: collision detection FSMs: game states(falling, clearing, game over).
VGA Output (640×480 @ 60 Hz): Pixel clock ≈ 25.175 MHz; HSYNC/VSYNC mark line/frame end; RGB pixels stream between syncs. Controller displays tetromino + background.
BRAM Background Grid preloaded into BRAM. VGA fetches pixels while overlay logic inserts tetromino blocks.
Game Logic Piece controller: spawn, move, rotate. Collision detection: prevent overlap. Line clearing: detect and remove rows. FSMs: update speed, track states. Logic runs parallel with VGA rendering for real time play.